1. Field of the Invention
The present invention relates to a data driven type information processing apparatus and method. More particularly, the present invention relates to a configuration of a branching unit including a self-synchronous transfer control circuit and a data transfer control method.
2. Description of the Background Art
Multi-media data processing that contains images requires a large amount of data to be processed at high speed. Particularly, the need arises for high-speed execution of a large amount of operations in image processing. A data driven type information processing apparatus is proposed as a processor accommodating such needs.
A data driven type information processing apparatus executes a process only after all the input data required for a certain process are available and resources such as a processing unit required for that process has been allocated.
For example, a data transfer apparatus employing an asynchronous handshake method is used as a data driven type information processing apparatus. This handshaking method employed in a data driven type information processing apparatus is one method of data transfer for conducting data transfer autonomously by transmitting/receiving a transfer request signal requesting data transfer and a transfer permission signal indicating whether data transfer is permitted or not between circuit blocks to transfer data (referred to as “data transmission path” hereinafter). The transfer request signal is referred to as a “SEND” signal, and a transfer permission signal is referred to as an “ACK” signal, hereinafter.
The operation of a data driven type information processing apparatus is disclosed in, for example, Japanese Patent Laying-Open No. 2001-331472. The data driven type information processing apparatus disclosed in this publication will be described hereinafter.
FIG. 7 represents a configuration of a data packet applied conventionally and in the present invention.
Referring to FIG. 7, a data packet DP includes a destination node number field F1 storing a destination node number ND#, a generation number field F2 storing a generation number GN#, an instruction code field F3 storing an instruction code OPC, and a data-field F4 storing data DATA.
The generation number serves to identify data groups that are processed in parallel from each other. The destination node number serves to identify input data with the same generation number from each other. The instruction code serves to indicate the instruction to be applied on the data.
FIG. 8 represents a configuration of a data transmission path.
Referring to FIG. 8, a data transmission path 100 includes a self-synchronous type transfer control circuit (referred to as “C element” hereinafter) 101A, and a data holding circuit formed of a D type flip-flop (referred to as “pipeline register” hereinafter). The meaning of “self-synchronous” will be described in detail afterwards.
Upon receiving a SEND signal from an input node CI, C element 101A provides an ACK signal from an output node RO. C element 101A also provides a SEND signal from output node CO, and receives an ACK signal at an input node RI. The operation and configuration of C element 101A will be described afterwards.
Pipeline register 101B receives a clock pulse provided from an output node CP of C element 101A to input and output a data packet.
FIG. 9 is a waveform diagram of signals input to and output from respective nodes of C element 101A of FIG. 8.
At time t1-t3, the SEND signal applied to input node CI attains an L level (logical low), whereby C element 101A receives a data packet transfer request. At time t2, C element 101A pulls down the ACK signal output from output node RO to an L level to inhibit reception of an additional data packet.
When the SEND signal applied to input node CI attains an H level (logical high) at time t3, input of a data packet to pipeline register 101B of FIG. 8 is completed. At time t4, the ACK signal from output node RO attains an H level indicating that data packet transfer is permitted, whereby C element 101A allows input of a data packet again.
At time t5, C element 101A pulls down the SEND signal that is to be output from output node CO to an L level to request transfer of a data packet, whereby output of the data packet is initiated.
When the clock pulse from output node CP is switched to an L level at time t7, the SEND signal from output node CO attains an H level at time t8. Thus, an output operation of a data packet ends.
As described above, data transfer control carried out in an asynchronous manner with at least a preset delay time in accordance with signals SEND and ACK is referred to as “self-synchronous transfer control”, and a circuit that conducts self-synchronous transfer control is referred to as “self-synchronous transfer control circuit”.
FIG. 10 represents an application of a data transmission path in a data driven type information processing apparatus.
Referring to FIG. 10, a data packet is sequentially transferred from pipeline register 104A to pipeline registers 104B and 104C. During such transfer, the data packet is processed by logic circuits 103A and 103B.
A data packet is not transmitted from pipeline register 104A to pipeline register 104B during the period of time pipeline register 104B retains a data packet. In the event of pipeline register 104B not retaining a data packet or just at the stage of data packet output, a data packet is transferred from pipeline register 104A to logic circuit 103A, and then to pipeline register 104B.
FIG. 11 represents a specific circuit configuration of C element 101A. Referring to FIG. 11, C element 101A includes a flip-flop 105A, an inverter 105G inverting the signal provided from an output Q of flip-flop 105A, and a flip-flop 105B providing a signal from an output node CP via a delay circuit 105E when set, and providing a signal from an output node CO when reset.
Flip-flop 105A is set upon receiving a SEND signal of an L level from the C element of the preceding stage not shown to provide a signal from output Q. The output signal is inverted by inverter 105G to become the ACK signal towards the C element of the preceding stage.
Flip-flop 105B is set upon receiving a signal of an L level from a NAND circuit 105C. When flip-flop 105B is set, a signal is provided from output node CP. The output signal from output node CP functions as a control signal of data output with respect to the pipeline register of a succeeding stage. When flip-flop 105B is reset, a signal is provided from output node CO, which becomes the SEND signal towards the C element of the succeeding stage.
NAND circuit 105C receives the SEND signal from the C element of the preceding stage through input node CI, and the ACK signal from the C element of the succeeding stage through input node RI. Furthermore, NAND circuit 105C receives a signal that is output when flip-flop 105B is reset, and a signal from output Q of flip-flop 105A.
FIG. 12 is a block diagram of a 2-input 2-output type router employed in a data driven type information processing apparatus of prior art and the present invention. A router is a device employed in the transfer of a data packet between processing units as well as between a processing unit and an external source.
Referring to FIG. 12, a router 106 includes branching units 106A and 106B, and junction units 106C and 106D.
A data packet applied to an input node IN1 is provided from either an output node OUT1 or an output node OUT2. Similarly, a data packet applied to an input node IN2 is provided from output node OUT1 or output node OUT2.
FIG. 13 is a block diagram of a conventional branching unit 106A of FIG. 12.
Referring to FIG. 13, branching unit 106A includes a branching control unit 107. Branching control unit 107 includes a C element 107A, an OR circuit 107C receiving a branching permission signal BEIN applied at an input node BE to indicate the branch destination of a data packet and a SEND signal from C element 107A, a logic gate 107D, and an AND circuit 107E receiving an ACK signal from junction units 106C and 106D shown in FIG. 12. The SEND signal is applied from output node COA to junction unit 106C, as well as from an output node COB to junction unit 106D.
To which of junction units 106C and 106D in FIG. 12 the SEND signal is to be transmitted is specified by branching permission signal BEIN. Depending upon whether branching permission signal BEIN attains an L level or H level, a SEND signal of an L level indicative of a transfer request is provided from either output node COA or output node COB.
The ACK signal indicating permission of transfer is applied to AND circuit 107E from input nodes RIA and RIB. A signal of an H level is output from AND circuit 107E in response to the ACK signals from respective branch destinations both attaining an H level representing a data transfer permitted state. The H level signal output from AND circuit 107E is applied to input node RI of C element 107A. Thus, C element 107A receives permission of data transfer.
FIG. 14 represents a specific example of C element 107A of branching control unit 107 of FIG. 13. Referring to FIG. 14, branching control unit 107 includes C element 107A. The configuration of C element 107A is similar to that of C element 101A of FIG. 11.
FIG. 15 is a waveform diagram of signals shown in FIG. 14.
Referring to FIG. 15, the operation of branching control unit 107 during time t1-t4 is similar to that of C element 101A of FIG. 9. Therefore, description thereof will not be repeated.
When ACK signals ACKIN1 and ACKIN2 both attain an H level at time t5, ACK signal ACKIN of an H level indicating transfer permission is applied to input node RI of C element 107A at time t6.
At time t9, SEND signal SNDOT1 of an L level is provided from output node COA to junction unit 106C of FIG. 12, whereby output of a data packet is initiated.
FIG. 16 is a block diagram of a conventional 1-input 4-output branching unit constituting another router.
Referring to FIG. 16, a branching unit 109 includes a C element 109A, an OR circuit 109F and logic gates 109G-109I receiving a branching permission signal applied through input nodes BEA and BEB and a SEND signal from C element 109A, and an AND circuit 109J receiving an ACK signal from respective branch destinations.
Likewise the branching control unit of FIG. 13, the transmission destination of a SEND signal is determined in accordance with a combination of the logic levels of branching permission signals applied to input nodes BEA and BEB.
The ACK signal from each branch destination applied through input nodes RIA, RIB, RIC and RID is applied to AND circuit 109J. Likewise AND circuit 107E of FIG. 13, AND circuit 109J outputs a signal of an H level in response to the ACK signals from respective branch destinations attaining an H level indicating a data transfer permitted state. C element 107A receives an ACK signal of an H level indicating permission of data transfer from AND circuit 109J.
At the conventional branching unit disclosed in Japanese Patent Laying-Open No. 2001-331472, output of a SEND signal from a C element to the branch destination will not be initiated unless all the plurality of branch destinations of data attain a data transfer permitted state.
As shown in the timing chart of FIG. 15, for example, SEND signal SNDIN attains an H level at time t3, and input of a data packet is completed. Since ACK signal ACKIN1 attains an H level at time t3, junction unit 106C of FIG. 12 attains a data input allowable state at time t3. However, since SEND signal SNDOT1 of an L level is not transmitted to junction unit 106C until time t9, transfer is not requested. Therefore, a data packet waiting state occurs at a conventional branching unit, posing the problem of data retention.